Datasheet

30.8.11 Status

Name: STATUS

Offset: 0x0F

Reset: 0x08

Property: -

Bit 7 6 5 4 3 2 1 0

SYNCBUSY SLAVE STOP

Access

R R R

Reset 0 0 1

Bit 7 – SYNCBUSY Synchronization Busy

This bit is cleared when the synchronization of registers between the clock domains is complete.

This bit is set when the synchronization of registers between clock domains is started.

Bit 4 – SLAVE Slave Status Flag

This bit is only available in 32-bit mode on the slave TC (i.e., TC5 and/or TC7). The bit is set when the

associated master TC (TC4 and TC6, respectively) is set to run in 32-bit mode.

Bit 3 – STOP Stop Status Flag

This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when

the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is '1'.

Value Description

Counter is running.

Counter is stopped.

30.8.12 Counter Value

SAM D21 Family

TC – Timer/Counter

Datasheet Complete

DS40001882D-page 696