Datasheet

30.8.10 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x0E
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
MCx MCx SYNCRDY ERR OVF
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bits 5,4 – MCx Match or Capture Channel x [x = 1..0]
This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture
value. This flag is set on the next CLK_TC_CNT cycle, and will generate an interrupt request if the
corresponding Match or Capture Channel x Interrupt Enable bit in the Interrupt Enable Set register
(INTENSET.MCx) is '1'.
Writing a '0' to one of these bits has no effect.
Writing a '1' to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag
In capture operation, this flag is automatically cleared when CCx register is read.
Bit 3 – SYNCRDY Synchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables
the Synchronization Ready interrupt.
Value Description
0
The Synchronization Ready interrupt is disabled.
1
The Synchronization Ready interrupt is enabled.
Bit 1 – ERR Error Interrupt Flag
This flag is set when a new capture occurs on a channel while the corresponding Match or Capture
Channel x interrupt flag is set, in which case there is nowhere to store the new capture.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Error interrupt flag.
Bit 0 – OVF Overflow Interrupt Flag
This flag is set on the next CLK_TC_CNT cycle after an overflow condition occurs, and will generate an
interrupt request if INTENCLR.OVF or INTENSET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
SAM D21 Family
TC – Timer/Counter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 695