Datasheet

30.8.8 Interrupt Enable Clear
Name: INTENCLR
Offset: 0x0C
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 7 6 5 4 3 2 1 0
MCx MCx SYNCRDY ERR OVF
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bits 5,4 – MCx Match or Capture Channel x Interrupt Enable [x = 1..0]
Writing a '0' to these bits has no effect.
Writing a '1' to MCx will clear the corresponding Match or Capture Channel x Interrupt Enable bit, which
disables the Match or Capture Channel x interrupt.
Value Description
0
The Match or Capture Channel x interrupt is disabled.
1
The Match or Capture Channel x interrupt is enabled.
Bit 3 – SYNCRDY Synchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables
the Synchronization Ready interrupt.
Value Description
0
The Synchronization Ready interrupt is disabled.
1
The Synchronization Ready interrupt is enabled.
Bit 1 – ERR Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value Description
0
The Error interrupt is disabled.
1
The Error interrupt is enabled.
Bit 0 – OVF Overflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt
request.
Value Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
SAM D21 Family
TC – Timer/Counter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 693