Datasheet

12. Peripherals Configuration Summary
Table 12-1. Peripherals Configuration Summary
Periph.
Name
Base
Address
IRQ
Line
AHB Clock APB Clock Generic Clock PAC Events DMA
Index Enabled
at Reset
Index Enabled
at Reset
Index Index Prot.
at Reset
User Generator Index Sleep
Walking
AHB-APB
Bridge A
0x40000000 0 Y
PAC0 0x40000000 0 Y
PM 0x40000400 0 1 Y 1 N Y
SYSCTRL 0x40000800 1 2 Y 0: DFLL48M
reference
1: FDPLL96M clk source
2: FDPLL96M 32kHz
2 N Y
GCLK 0x40000C00 3 Y 3 N Y
WDT 0x40001000 2 4 Y 3 4 N
RTC 0x40001400 3 5 Y 4 5 N 1: CMP0/ALARM0
2: CMP1
3: OVF
4-11: PER0-7
Y
EIC 0x40001800 NMI,
4
6 Y 5 6 N 12-27: EXTINT0-15 Y
AHB-APB
Bridge B
0x41000000 1 Y
PAC1 0x41000000 0 Y
DSU 0x41002000 3 Y 1 Y 1 Y
NVMCTRL 0x41004000 5 4 Y 2 Y 2 N
PORT 0x41004400 3 Y 3 N
DMAC 0x41004800 6 5 Y 4 Y 4 N 0-3: CH0-3 30-33: CH0-3
USB 0x41005000 7 6 Y 5 Y 6 5 N Y
MTB 0x41006000 6 N
AHB-APB
Bridge C
0x42000000 2 Y
PAC2 0x42000000 0 N
EVSYS 0x42000400 8 1 N 7-18: one per CHANNEL 1 N Y
SERCOM0 0x42000800 9 2 N 20: CORE
19: SLOW
2 N 1: RX
2: TX
Y
SERCOM1 0x42000C00 10 3 N 21: CORE
19: SLOW
3 N 3: RX
4: TX
Y
SERCOM2 0x42001000 11 4 N 22: CORE
19: SLOW
4 N 5: RX
6: TX
Y
SERCOM3 0x42001400 12 5 N 23: CORE
19: SLOW
5 N 7: RX
8: TX
Y
SERCOM4 0x42001800 13 6 N 24: CORE
19: SLOW
6 N 9: RX
10: TX
Y
SERCOM5 0x42001C00 14 7 N 25: CORE
19: SLOW
7 N 11: RX
12: TX
Y
TCC0 0x42002000 15 8 N 26 8 N 4-5: EV0-1
6-9: MC0-3
34: OVF
35: TRG
36: CNT
37-40: MC0-3
13: OVF
14-17: MC0-3
Y
TCC1 0x42002400 16 9 N 26 9 N 10-11: EV0-1
12-13: MC0-1
41: OVF
42: TRG
43: CNT
44-45: MC0-1
18: OVF
19-20: MC0-1
Y
TCC2 0x42002800 17 10 N 27 10 N 14-15: EV0-1
16-17: MC0-1
46: OVF
47: TRG
48: CNT
49-50: MC0-1
21: OVF
22-23: MC0-1
Y
TC3 0x42002C00 18 11 N 27 11 N 18: EV 51: OVF
52-53: MC0-1
24: OVF
25-26: MC0-1
Y
SAM D21 Family
Peripherals Configuration Summary
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 69