Datasheet

30.8.4 Control B Set
Name: CTRLBSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection, Read-synchronized, Write-Synchronized
This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation.
Changes in this register will also be reflected in the Control B Clear register (CTRLBCLR).
Bit 7 6 5 4 3 2 1 0
CMD[1:0] ONESHOT DIR
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bits 7:6 – CMD[1:0] Command
These bits are used for software control of the TC. The commands are executed on the next prescaled
GCLK_TC clock cycle. When a command has been executed, the CMD bit group will be read back as
zero.
Writing 0x0 to these bits has no effect.
Writing a '1' to one of these bits will set a command.
Table 30-9. Command
Value Name Description
0x0 NONE No action
0x1 RETRIGGER Force a start, restart or retrigger
0x2 STOP Force a stop
0x3 - Reserved
Bit 2 – ONESHOT One-Shot on Counter
This bit controls one-shot operation of the TC.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will enable one-shot operation.
Value Description
0
The TC will wrap around and continue counting on an Overflow/Underflow condition.
1
The TC will wrap around and stop on the next Underflow/Overflow condition.
Bit 0 – DIR Counter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will make the counter count down.
Value Description
0
The timer/counter is counting up (incrementing).
SAM D21 Family
TC – Timer/Counter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 687