Datasheet

Value Name Description
0x7
DIV1024 Prescaler: GCLK_TC/1024
Bits 6:5 – WAVEGEN[1:0] Waveform Generation Operation
These bits select the waveform generation operation. They affect the top value, as shown in “Waveform
Output Operations”. It also controls whether frequency or PWM waveform generation should be used.
How these modes differ can also be seen from “Waveform Output Operations”.
These bits are not synchronized.
Table 30-7. Waveform Generation Operation
Value Name Operation Top Value Waveform
Output on
Match
Waveform
Output on
Wraparound
0x0 NFRQ Normal
frequency
PER
(1)
/Max Toggle No action
0x1 MFRQ Match
frequency
CC0 Toggle No action
0x2 NPWM Normal PWM PER
(1)
/Max Clear when
counting up Set
when counting
down
Set when
counting up
Clear when
counting down
0x3 MPWM Match PWM CC0 Clear when
counting up Set
when counting
down
Set when
counting up
Clear when
counting down
Note:
1. This depends on the TC mode. In 8-bit mode, the top value is the Period Value register (PER). In
16- and 32-bit mode it is the maximum value.
Bits 3:2 – MODE[1:0] Timer Counter Mode
These bits select the counter mode.
These bits are not synchronized.
Value Name Description
0x0
COUNT16 Counter in 16-bit mode
0x1
COUNT8 Counter in 8-bit mode
0x2
COUNT32 Counter in 32-bit mode
0x3
- Reserved
Bit 1 – ENABLE Enable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRLA.ENABLE will read back immediately, and the ENABLE
Synchronization Busy bit in the SYNCBUSY register (SYNCBUSY.ENABLE) will be set.
SYNCBUSY.ENABLE will be cleared when the operation is complete.
This bit is not enable protected.
SAM D21 Family
TC – Timer/Counter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 682