Datasheet

• Enable bit in the Control A register (CTRLA.ENABLE)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register
description.
The following registers are synchronized when written:
• Control B Clear register (CTRLBCLR)
• Control B Set register (CTRLBSET)
• Control C register (CTRLC)
• Count Value register (COUNT)
• Period Value register (PER)
• Compare/Capture Value registers (CCx)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register
description.
The following registers are synchronized when read:
• Control B Clear register (CTRLBCLR)
• Control B Set register (CTRLBSET)
• Control C register (CTRLC)
• Count Value register (COUNT)
• Period Value register (PER)
• Compare/Capture Value registers (CCx)
Required read-synchronization is denoted by the "Read-Synchronized" property in the register
description.
Related Links
14.3 Register Synchronization
30.7 Register Summary
Table 30-4. Register Summary – 8-bit Mode
Offset Name Bit Pos.
0x00
CTRLA
7:0 WAVEGEN[1:0] MODE[1:0] ENABLE SWRST
0x01 15:8 PRESCSYNC[1:0] RUNSTDBY PRESCALER[2:0]
0x02
READREQ
7:0 ADDR[4:0]
0x03 15:8 RREQ RCONT
0x04 CTRLBCLR 7:0 CMD[1:0] ONESHOT DIR
0x05 CTRLBSET 7:0 CMD[1:0] ONESHOT DIR
0x06 CTRLC 7:0 CPTEN1 CPTEN0 INVEN1 INVEN0
0x07 Reserved
0x08 DBGCTRL 7:0 DBGRUN
0x09 Reserved
0x0A
EVCTRL
7:0 TCEI TCINV EVACT[2:0]
0x0B 15:8 MCEO1 MCEO0 OVFEO
0x0C INTENCLR 7:0 MC1 MC0 SYNCRDY ERR OVF
0x0D INTENSET 7:0 MC1 MC0 SYNCRDY ERR OVF
SAM D21 Family
TC – Timer/Counter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 677