Datasheet

Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable
Set register (INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable
Clear register (INTENCLR).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or
the TC is reset. on how to clear interrupt flags.
The TC has one common interrupt request line for all the interrupt sources. The user must read the
INTFLAG register to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested
Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
30.6.4.3 Events
The TC can generate the following output events:
• Overflow/Underflow (OVF)
• Match or Capture (MC)
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.MCEOx) enables the
corresponding output event. The output event is disabled by writing EVCTRL.MCEOx=0.
One of the following event actions can be selected by the Event Action bit group in the Event Control
register (EVCTRL.EVACT):
• Start TC (START)
• Re-trigger TC (RETRIGGER)
• Increment or decrement counter (depends on counter direction)
• Count on event (COUNT)
• Capture Period (PPW and PWP)
Writing a '1' to the TC Event Input bit in the Event Control register (EVCTRL.TCEI) enables input events
to the TC. Writing a '0' to this bit disables input events to the TC. The TC requires only asynchronous
event inputs. For further details on how configuring the asynchronous events, refer to EVSYS - Event
System.
Related Links
24. EVSYS – Event System
30.6.5 Sleep Mode Operation
The TC can be configured to operate in any sleep mode. To be able to run in standby, the RUNSTDBY bit
in the Control A register (CTRLA.RUNSTDBY) must be written to one. The TC can wake up the device
using interrupts from any sleep mode or perform actions through the Event System.
30.6.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following bits are synchronized when written:
• Software Reset bit in the Control A register (CTRLA.SWRST)
SAM D21 Family
TC – Timer/Counter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 676