Datasheet

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Condition Interrupt
request
Event output Event input DMA request DMA request
is cleared
Capture
Overflow Error
YES
Synchronizatio
n Ready
YES
Start Counter YES
Retrigger
Counter
YES
Increment /
Decrement
counter
YES
Simple Capture YES
Period Capture YES
Pulse Width
Capture
YES
Note: 1. Two DMA requests lines are available, one for each compare/capture channel.
30.6.4.1 DMA Operation
The TC can generate the following DMA requests:
• Overflow (OVF): the request is set when an update condition (overflow, underflow) is detected. The
request is cleared on next clock cycle.
• Channel Match or Capture (MCx): for a compare channel, the request is set on each compare
match detection and cleared on next clock cycle. For a capture channel, the request is set when
valid data is present in CCx register, and cleared when CCx register is read.
When using the TC with the DMA OVF request, the new value will be transferred to the register after the
update condition. This means that the value is updated after the DMA and synchronization delay, and if
the COUNT value has reached the new value before PER or CCx is updated, a match will not happen.
When using the TC with the DMA MCx request and updating CCx with a value that is lower than the
current COUNT when down-counting, or higher than the current COUNT when up-counting, this value
could cause a new compare match before the counter overflows. This will trigger the next DMA transfer,
update CCx again, and the previous value is disregarded from the output signal WO[x].
30.6.4.2 Interrupts
The TC has the following interrupt sources:
• Overflow/Underflow (OVF)
• Match or Capture Channel x (MCx)
• Capture Overflow Error (ERR)
• Synchronization Ready (SYNCRDY)
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear register (INTFLAG) is set when the interrupt condition occurs.
SAM D21 Family
TC – Timer/Counter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 675