Datasheet

Figure 30-10. PWP Capture
Period (T)
external signal
events
COUNT
MAX
ZERO
"capture"
Pulsewitdh (t
p
)
CC0 CC0 CC1CC1
30.6.3 Additional Features
30.6.3.1 One-Shot Operation
When one-shot is enabled, the counter automatically stops on the next counter overflow or underflow
condition. When the counter is stopped, the Stop bit in the Status register (STATUS.STOP) is
automatically set and the waveform outputs are set to zero.
One-shot operation is enabled by writing a '1' to the One-Shot bit in the Control B Set register
(CTRLBSET.ONESHOT), and disabled by writing a '1' to CTRLBCLR.ONESHOT. When enabled, the TC
will count until an overflow or underflow occurs and stops counting operation. The one-shot operation can
be restarted by a re-trigger software command, a re-trigger event, or a start event. When the counter
restarts its operation, STATUS.STOP is automatically cleared.
30.6.4 DMA, Interrupts and Events
Table 30-3. Module Request for TC
Condition Interrupt
request
Event output Event input DMA request DMA request
is cleared
Overflow /
Underflow
YES YES YES Cleared on next
clock cycle
Channel
Compare
Match or
Capture
YES YES YES
1
For compare
channel –
Cleared on next
clock cycle.
For capture
channel –
cleared when
CCx register is
read
SAM D21 Family
TC – Timer/Counter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 674