Datasheet
For single-slope PWM generation, the period time (T) is controlled by the TOP value, and CCx controls
the duty cycle of the generated waveform output. When up-counting, the WO[x] is set at start or compare
match between the COUNT and TOP values, and cleared on compare match between COUNT and CCx
register values. When down-counting, the WO[x] is cleared at start or compare match between the
COUNT and ZERO values, and set on compare match between COUNT and CCx register values.
The following equation calculates the exact resolution for a single-slope PWM (R
PWM_SS
) waveform:
PWM_SS
=
log(TOP+1)
log(2)
The PWM frequency (f
PWM_SS
) depends on TOP value and the peripheral clock frequency (f
GCLK_TC
), and
can be calculated by the following equation:
PWM_SS
=
GCLK_TC
N(TOP+1)
Where N represents the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024).
Match Pulse-Width Modulation Operation (MPWM)
In MPWM, the output of WO[1] is depending on CC1 as shown in the figure below. On every overflow/
underflow, a one-TC-clock-cycle negative pulse is put out on WO[0] (not shown in the figure).
Figure 30-6. Match PWM Operation
COUNT
MAX
CC0
Period (T)
" match"
ZERO
CCx= Zero
CC1
CCx= TOP
" clear" update
WO[1]
The table below shows the update counter and overflow event/interrupt generation conditions in different
operation modes.
Table 30-2. Counter Update and Overflow Event/interrupt Conditions in TC
Name Operation TOP Update Output Waveform OVFIF/Event
On Match On Update Up Down
NFRQ Normal Frequency PER TOP/ ZERO Toggle Stable TOP ZERO
MFRQ Match Frequency CC0 TOP/ ZERO Toggle Stable TOP ZERO
NPWM Single-slope PWM PER TOP/ ZERO See description above. TOP ZERO
MPWM Single-slope PWM CC0 TOP/ ZERO Toggle Toggle TOP ZERO
30.6.2.6.4 Changing the Top Value
The counter period is changed by writing a new TOP value to the Period register (PER or CC0,
depending on the waveform generation mode). If a new TOP value is written when the counter value is
close to zero and counting down, the counter can be reloaded with the previous TOP value, due to
synchronization delays. Then, the counter will count one extra cycle before the new TOP value is used.
SAM D21 Family
TC – Timer/Counter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 671