Datasheet

3. Select one wave generation operation in the Waveform Generation Operation bit group in the
Control A register (CTRLA.WAVEGEN).
4. If desired, the GCLK_TCx clock can be prescaled via the Prescaler bit group in the Control A
register (CTRLA.PRESCALER).
– If the prescaler is used, select a prescaler synchronization operation via the Prescaler and
Counter Synchronization bit group in the Control A register (CTRLA.PRESYNC).
5. Select one-shot operation by writing a '1' to the One-Shot bit in the Control B Set register
(CTRLBSET.ONESHOT).
6. If desired, configure the counting direction 'down' (starting from the TOP value) by writing a '1' to
the Counter Direction bit in the Control B register (CTRLBSET.DIR).
7. For capture operation, enable the individual channels to capture in the Capture Channel x Enable
bit group in the Control C register (CTRLC.CPTEN).
8. If desired, enable inversion of the waveform output or IO pin input signal for individual channels via
the Waveform Output Invert Enable bit group in the Control C register (CTRLC.INVEN).
30.6.2.2 Enabling, Disabling and Resetting
The TC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The TC is
disbled by writing a zero to CTRLA.ENABLE.
The TC is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All
registers in the TC, except DBGCTRL, will be reset to their initial state, and the TC will be disabled. Refer
to the CTRLA register for details.
The TC should be disabled before the TC is reset in order to avoid undefined behavior.
30.6.2.3 Prescaler Selection
The GCLK_TCx is fed into the internal prescaler.
The prescaler consists of a counter that counts up to the selected prescaler value, whereupon the output
of the prescaler toggles.
If the prescaler value is higher than one, the counter update condition can be optionally executed on the
next GCLK_TCx clock pulse or the next prescaled clock pulse. For further details, refer to Prescaler
(CTRLA.PRESCALER) and Counter Synchronization (CTRLA.PRESYNC) description.
Prescaler outputs from 1 to 1/1024 are available. For a complete list of available prescaler outputs, see
the register description for the Prescaler bit group in the Control A register (CTRLA.PRESCALER).
Note: When counting events, the prescaler is bypassed.
The joint stream of prescaler ticks and event action ticks is called CLK_TC_CNT.
Figure 30-2. Prescaler
PRESCALER
GCLK_TC /
{1,2,4,8,64,256,1024}
GCLK_TC
Prescaler
COUNT
CLK_TC_CNT
EVACT
EVENT
30.6.2.4 Counter Mode
The counter mode is selected by the Mode bit group in the Control A register (CTRLA.MODE). By default,
the counter is enabled in the 16-bit counter resolution. Three counter resolutions are available:
SAM D21 Family
TC – Timer/Counter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 667