Datasheet

11.2 Nested Vector Interrupt Controller
30.5.6 Events
The events of this peripheral are connected to the Event System.
Related Links
24. EVSYS – Event System
30.5.7 Debug Operation
When the CPU is halted in debug mode, this peripheral will halt normal operation. This peripheral can be
forced to continue operation during debugging - refer to the Debug Control (DBGCTRL) register for
details.
30.5.8 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC),
except for the following:
• Interrupt Flag register (INTFLAG)
• Status register (STATUS)
• Read Request register (READREQ)
• Count register (COUNT)
• Period register (PER)
• Compare/Capture Value registers (CCx)
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
Write-protection does not apply for accesses through an external debugger.
30.5.9 Analog Connections
Not applicable.
30.6 Functional Description
30.6.1 Principle of Operation
The following definitions are used throughout the documentation:
Table 30-1. Timer/Counter Definitions
Name Description
TOP The counter reaches TOP when it becomes equal to the highest value in
the count sequence. The TOP value can be the same as Period (PER)
or the Compare Channel 0 (CC0) register value depending on the
waveform generator mode in Waveform Output Operations.
ZERO The counter is ZERO when it contains all zeroes
MAX The counter reaches MAX when it contains all ones
UPDATE The timer/counter signals an update when it reaches ZERO or TOP,
depending on the direction settings.
SAM D21 Family
TC – Timer/Counter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 665