Datasheet

29.9.8 Data Holding m
Name: DATAm
Offset: 0x30 + m*0x04 [m=0..1]
Reset: 0x00000000
Property: Read-Synchronized, Write-Synchronized
Bit 31 30 29 28 27 26 25 24
DATA[31:24]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DATA[23:16]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DATA[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 31:0 – DATA[31:0] Sample Data
This register is used to transfer data to or from Serializer n.
Data samples written to DATAn register will be sent to Serializer n for transmission, through the Transmit
Formatting Unit that will apply the formatting specified in the SERCTRLn register.
Data samples received by Serializer n will be available for reading from DATAn register, through the
Receive Formatting Unit, according to formatting information for Serializer n in the SERCTRLn register.
SAM D21 Family
I2S - Inter-IC Sound Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 660