Datasheet

29.9.6 Synchronization Busy
Name: SYNCBUSY
Offset: 0x18
Reset: 0x0000
Property: -
Bit 15 14 13 12 11 10 9 8
DATAx DATAx
Access
R R
Reset 0 0
Bit 7 6 5 4 3 2 1 0
SERENx SERENx CKENx CKENx ENABLE SWRST
Access
R R R R R R
Reset 0 0 0 0 0 0
Bits 8,9 – DATAx Data x Synchronization Status [x=1..0]
Bit DATAx is cleared when the synchronization of DATA Holding register (DATAx) between the clock
domains is complete.
Bit DATAx is set when the synchronization of DATA Holding register (DATAx) between the clock domains
is started.
Bits 4,5 – SERENx Serializer x Enable Synchronization Status [x=1..0]
Bit SERENx is cleared when the synchronization of CTRLA.SERENx bit between the clock domains is
complete.
Bit SERENx is set when the synchronization of CTRLA.SERENx bit between the clock domains is started.
Bits 2,3 – CKENx Clock Unit x Enable Synchronization Status [x=1..0]
Bit CKENx is cleared when the synchronization of CTRLA.CKENx bit between the clock domains is
complete.
Bit CKENx is set when the synchronization of CTRLA.CKENx bit between the clock domains is started.
Bit 1 – ENABLE Enable Synchronization Status
This bit is cleared when the synchronization of CTRLA.ENABLE bit between the clock domains is
complete.
This bit is set when the synchronization of CTRLA.ENABLE bit between the clock domains is started.
Bit 0 – SWRST Software Reset Synchronization Status
This bit is cleared when the synchronization of CTRLA.SWRST bit between the clock domains is
complete.
This bit is set when the synchronization of CTRLA.SWRST bit between the clock domains is started.
SAM D21 Family
I2S - Inter-IC Sound Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 655