Datasheet

29.9.4 Interrupt Enable Set
Name:  INTENSET
Offset:  0x10
Reset:  0x0000
Property:  PAC Write-Protection
Bit 15 14 13 12 11 10 9 8
TXURx TXURx TXRDYx TXRDYx
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RXORx RXORx RXRDYx RXRDYx
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bits 13,12 – TXURx  Transmit Underrun x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Transmit Underrun Interrupt Enable bit, which enables the Transmit
Underrun interrupt.
Value Description
0
The Transmit Underrun interrupt is disabled.
1
The Transmit Underrun interrupt is enabled.
Bits 9,8 – TXRDYx  Transmit Ready x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Transmit Ready Interrupt Enable bit, which enables the Transmit Ready
interrupt.
Value Description
0
The Transmit Ready interrupt is disabled.
1
The Transmit Ready interrupt is enabled.
Bits 4,5 – RXORx  Receive Overrun x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Receive Overrun Interrupt Enable bit, which enables the Receive
Overrun interrupt.
Value Description
0
The Receive Overrun interrupt is disabled.
1
The Receive Overrun interrupt is enabled.
Bits 1,0 – RXRDYx  Receive Ready x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
SAM D21 Family
I2S - Inter-IC Sound Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 651