Datasheet

Bits 23:19 – MCKDIV[4:0] Master Clock Division Factor

The Master Clock n is divided by (MCKDIV + 1) to obtain the Serial Clock n.

Bit 18 – MCKEN Master Clock Enable

Value Description

The Master Clock n division and output is disabled.

The Master Clock n division and output is enabled.

Bit 16 – MCKSEL Master Clock Select

This field selects the source of the Master Clock n.

MCKSEL Name Description

0x0 GCLK GCLK_I2S_n is used as Master Clock n source

0x1 MCKPIN MCKn input pin is used as Master Clock n source

Bit 12 – SCKSEL Serial Clock Select

This field selects the source of the Serial Clock n.

SCKSEL Name Description

0x0 MCKDIV Divided Master Clock n is used as Serial Clock n source

0x1 SCKPIN SCKn input pin is used as Serial Clock n source

Bit 11 – FSINV Frame Sync Invert

Value Description

The Frame Sync n is used without inversion.

The Frame Sync n is inverted before being used.

Bit 8 – FSSEL Frame Sync Select

This field selects the source of the Frame Sync n.

FSSEL Name Description

0x0 SCKDIV Divided Serial Clock n is used as Frame Sync n source

0x1 FSPIN FSn input pin is used as Frame Sync n source

Bit 7 – BITDELAY Data Delay from Frame Sync

BITDELAY Name Description

0x0 LJ Left Justified (0 Bit Delay)

0x1 I2S I2S (1 Bit Delay)

Bits 6:5 – FSWIDTH[1:0] Frame Sync Width

This field selects the duration of the Frame Sync output pulses.

When not in Burst mode, the Clock unit n operates in continuous mode when enabled, with periodic

Frame Sync pulses and Data samples.

SAM D21 Family

I2S - Inter-IC Sound Controller

Datasheet Complete

DS40001882D-page 647