Datasheet

29.9.2 Clock Unit n Control
Name: CLKCTRLn
Offset: 0x04 + n*0x04 [n=0..1]
Reset: 0x00000000
Property: Enable-Protected, PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
MCKOUTINV SCKOUTINV FSOUTINV MCKOUTDIV[4:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
MCKDIV[4:0] MCKEN MCKSEL
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
SCKSEL FSINV FSSEL
Access
R/W R/W R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
BITDELAY FSWIDTH[1:0] NBSLOTS[2:0] SLOTSIZE[1:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 31 – MCKOUTINV Master Clock Output Invert
Value Description
0
The Master Clock n is output without inversion.
1
The Master Clock n is inverted before being output.
Bit 30 – SCKOUTINV Serial Clock Output Invert
Value Description
0
The Serial Clock n is output without inversion.
1
The Serial Clock n is inverted before being output.
Bit 29 – FSOUTINV Frame Sync Output Invert
Value Description
0
The Frame Sync n is output without inversion.
1
The Frame Sync n is inverted before being output.
Bits 28:24 – MCKOUTDIV[4:0] Master Clock Output Division Factor
The generic clock selected by MCKSEL is divided by (MCKOUTDIV + 1) to obtain the Master Clock n
output.
SAM D21 Family
I2S - Inter-IC Sound Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 646