Datasheet

ManualsBrandsMicrochip ManualsARM MicrocontrollersARM® Cortex® M0+ SAM Microcontroller 32bit 256KB TQFP

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individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET)

enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or

the I

S is reset. See INTFLAG register for details on how to clear interrupt flags. All interrupt requests

from the peripheral are ORed together on system level to generate one combined interrupt request to the

NVIC. Refer to Nested Vector Interrupt Controller for details. The user must read the INTFLAG register to

determine which interrupt condition is present.

Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector

Interrupt Controller for details.

Related Links

11.2 Nested Vector Interrupt Controller

29.6.8.3 Events

Not applicable.

29.6.9 Sleep Mode Operation

The I

S continues to operate in all sleep modes that still provide its clocks.

29.6.10 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers

need to be synchronized when written or read.

When executing an operation that requires synchronization, the corresponding Synchronization Busy bit

in the Synchronization Busy register (SYNCBUSY) will be set immediately, and cleared when

synchronization is complete.

If an operation that requires synchronization is executed while the corresponding SYNCBUSY bit is '1', a

peripheral bus error is generated.

The following bits are synchronized when written:

• Software Reset bit in the Control A register (CTRLA.SWRST). SYNCBUSY.SWRST is set to '1'

while synchronization is in progress.

• Enable bit in the Control A register (CTRLA.ENABLE). SYNCBUSY.ENABLE is set to '1' while

synchronization is in progress.

• Clock Unit x Enable bits in the Control A register (CTRLA.CKENx). SYNCBUSY.CKENx is set to '1'

while synchronization is in progress.

• Serializer x Enable bits in the Control A register (CTRLA.SERENx). SYNCBUSY.SERENx is set to

'1' while synchronization is in progress.

The following registers require synchronization when read or written:

• Data n registers (DATAn), Read-Synchronized when Serializer n is in Rx mode or Write-

Synchronized when in Tx mode. SYNCBUSY.DATAn is set to '1' while synchronization is in

progress.

Synchronization is denoted by the Read-Synchronized or Write-Synchronized property in the register

description.