Datasheet

• EXTEND for extension to the word size
29.6.8 DMA, Interrupts and Events
Table 29-4. Module Request for I
2
S
Condition DMA
request
DMA request is cleared Interrupt
request
Event input/
output
Receive Ready YES When data is read YES
Transmit Ready (Buffer
empty)
YES When data is written YES
Receive Overrun YES
Transmit Underrun YES
29.6.8.1 DMA Operation
Each Serializer can be connected either to one single DMAC channel or to one DMAC channel per data
slot in stereo mode. This is selected by writing the SERCTRLm.DMA bit:
Table 29-5. I
2
C DMA Request Generation
SERCTRLm.DMA Mode Slot Parity DMA Request Trigger
0 Receiver all I2S_DMAC_ID_RX_m
Transmitter all I2S_DMAC_ID_TX_m
1 Receiver even I2S_DMAC_ID_RX_0
odd I2S_DMAC_ID_RX_1
Transmitter even I2S_DMAC_ID_TX_0
odd I2S_DMAC_ID_TX_1
The DMAC reads from the DATAm register and writes to the DATAm register for all data slots,
successively.
The DMAC transfers may use 32-, 16- or or 8-bit transactions according to the value of the
SERCTRLm.DATASIZE field. 8-bit compact stereo uses 16-bit and 16-bit compact stereo uses 32-bit
transactions.
29.6.8.2 Interrupts
The I
2
S has the following interrupt sources:
• Receive Ready (RXRDYm): this is an asynchronous interrupt and can be used to wake-up the
device from any sleep mode.
• Receive Overrun (RXORm): this is an asynchronous interrupt and can be used to wake-up the
device from any sleep mode.
• Transmit Ready (TXRDYm): this is an asynchronous interrupt and can be used to wake-up the
device from any sleep mode.
• Transmit Underrun (TXURm): this is an asynchronous interrupt and can be used to wake-up the
device from any sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be
SAM D21 Family
I2S - Inter-IC Sound Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 638