Datasheet

Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the Serial
Clock. The FSn pin provides a frame synchronization signal, at the beginning of slot 0. The delay
between the frame start and the first data bit is defined by writing the CLKCTRLn.BITDELAY field.
The Frame Sync pulse can be either one SCKn period (BIT), one slot (SLOT), or one half frame (HALF).
This selection is done by writing the CLKCTRLn.FSWIDTH field.
The number of slots is selected by writing the CLKCTRLn.NBSLOTS field.
The number of bits in each slot is selected by writing the CLKCTRLn.SLOTSIZE field.
The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing the
DATASIZE field in the Serializer Control register (SERCTRLm).
If the slot allows more data bits than the number of bits specified in the SERCTRLmDATASIZE bit field,
additional bits are appended to the transmitted or received data word as specified in the
SERCTRLmEXTEND bit field. If the slot allows less data bits than programmed, the extra bits are not
transmitted, or received data word is extended based on the EXTEND field value.
29.6.6 PDM Reception
In Pulse Density Modulation (PDM) reception mode, continuous 1-bit data samples are available on the
SDI line on each SCKn rising edge, e.g. by a MEMS microphone with PDM interface. When using two
channel PDM microphones, the second one (right channel) is configured to output data on each SCKn
falling edge.
For one PDM microphone, the I
2
S controller should be configured in normal Receive mode with one slot
and 16- or 32-bit data size, so that 16 or 32 samples of the microphone are stored into each data word.
For two PDM microphones, the I
2
S controller should be configured in PDM2 mode with one slot and 32-
bit data size. The Serializer will store 16 samples of each microphone in one half of the data word, with
left microphone bits in lower half and right microphone bits in upper half, like in compact stereo format.
Based on oversampling frequency requirement from PDM microphone, the SCKn frequency must be
configured in the I
2
S controller.
A microphone that requires a sampling frequency of fs = 48 kHz and an oversampling
frequency of fo=64 × fs would require an SCKn frequency of 3.072 MHz.
After selecting a proper frequency for GCLK_I2S_n and according Master Clock Division Factor in the
Clock Unit n Control register (CLKCTRLn.MCKDIV), SCKn must be selected as per required frequency.
In PDM mode, only the clock and data line (SCKn and SDIn) pins are used.
To configure PDM2 mode, set SLOTSIZE = 0x01 (16-bits), NBSLOTS = 0x00 (1 slots) and
SERCTRL0.DATASIZE = 0x00 (32-bit).
29.6.7 Data Formatting Unit
To allow more flexibility, data words received by Serializer m will be formatted by the Receive Formatting
Unit before being stored into the Data Holding register (RXDATA). The data words written into TXDATA
register will be formatted by the Transmit Formatting Unit before transmission by Serializer m .
The formatting options are defined in SERCTRLm:
• SLOTADJ for left or right justification in the slot
• BITREV for bit reversal
• WORDADJ for left or right justification in the data word
SAM D21 Family
I2S - Inter-IC Sound Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 637