Datasheet

Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the Serial
Clock. The Word Select line indicates the channel in transmission, a low level for the left channel and a
high level for the right channel.
In I
2
S format, typical configurations are described below. These configurations do not list all necessary
settings, but only basic ones. Other configuration settings are to be done as per requirement such as
clock and DMA configurations.
Case 1: I
2
S 16-bit compact stereo
• Slot size configured as 16 bits (CLKCTRL0.SLOTSIZE = 0x1)
• Number of slots configured as 2 (CLKCTRL0.NBSLOTS = 0x1)
• Data size configured as 16-bit compact stereo (SERCTRL0.DATASIZE = 0x05)
• Data delay from Frame Sync configured as 1-bit delay (CLKCTRLn.BITDELAY = 0x01)
• Frame Sync Width configured as HALF frame (CLKCTRLn.FSWIDTH = 0x01)
Case 2: I
2
S 24-bit stereo Transmitterwith 24-bit slot
• Slot size configured as 24 bits (CLKCTRL0.SLOTSIZE = 0x2)
• Number of slots configured as 2 (CLKCTRL0.NBSLOTS = 0x1)
• Data size configured as 24 bits (SERCTRL0.DATASIZE = 0x01)
• Data delay from Frame Sync configured as 1-bit delay (CLKCTRLn.BITDELAY = 0x01)
• Frame Sync Width configured as HALF frame (CLKCTRLn.FSWIDTH = 0x01)
In both cases, it will ensure that Word select signal is 'low level' for the left channel and 'high level' for the
right channel.
The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing the Data
Word Size bit group in the Serializer Control mregister (SERCTRLm.DATASIZE).
If the slot allows for more data bits than the number of bits specified in the respective DATASIZE field,
additional bits are appended to the transmitted or received data word as specified in the
SERCTRLm.EXTEND field. If the slot allows less data bits than programmed, the extra bits are not
transmitted, or received data word is extended based on the EXTEND field value.
29.6.5 TDM Format - Reception and Transmission Sequence
In Time Division Multiplexed (TDM) format, the number of data slots sent or received within each frame
will be (CLKCTRLn.NBSLOTS + 1).
By configuring the CLKCTRLn register (CLKCTRLn.FSWIDTH and CLKCTRLn.FSINV), the Frame Sync
pulse width and polarity can be modified.
By configuring SERCTRLm, data bits can be left-adjusted or right-adjusted in the slot. It can also
configure the data transmission/reception with either the MSB or the LSB transmitted/received first and
starting the transmission/reception either at the transition of the FSn pin or one clock period after.
Figure 29-6. TDM Format Reception and Transmission Sequence
SAM D21 Family
I2S - Inter-IC Sound Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 636