Datasheet

The FSn pin is used as Word Select in I
2
S format and as Frame Synchronization in TDM format, as
described in 29.6.4 I2S Format - Reception and Transmission Sequence with Word Select and 29.6.5
TDM Format - Reception and Transmission Sequence, respectively.
29.6.2.2 Data Holding Registers
For each Serializer m, the I
2
S user interface includes a Data m register (DATAm). They are used to
access data samples for all data slots.
29.6.2.2.1 Data Reception Mode
In receiver mode, the DATAm registers store the received data.
When a new data word is available in the DATAm register, the Receive Ready bit (RXRDYm) in the
Interrupt Flag Status and Clear register (INTFLAG) is set. Reading the DATAm register will clear this bit.
A receive overrun condition occurs if a new data word becomes available before the previous data word
has been read from the DATAm register. Then, the Receive Overrun bit in INTFLAG will be set
(INTFLAG.RXORm). This interrupt can be cleared by writing a '1' to it.
29.6.2.2.2 Data Transmission Mode
In Transmitter mode, the DATAm registers contain the data to be transmitted.
when DATAm is empty, the Transmit Ready bit in the Interrupt Flag Status and Clear register is set
(INTFLAG.TXRDYm). Writing to DATAm will clear this bit.
A transmit underrun condition occurs if a new data word needs to be transmitted before it has been
written to DATAm. Then, the Transmit Underrun bit in INTFLAG will be set (INTFLAG.TXURm). This
interrupt can be cleared by writing a '1' to it. The Transmit Data when Underrun bit in the Serializer n
Control register (SERCTRLm.TXSAME) configures whether a zero data word is transmitted in case of
underrun (SERCTRLm.TXSAME=0), or the previous data word for the current transmit slot number is
transmitted again (SERCTRLm.TXSAME=1).
29.6.3 Master, Controller, and Slave Modes
In Master and Controller modes, the I
2
S provides the Serial Clock, a Word Select/Frame Sync signal and
optionally a Master Clock.
In Controller mode, the I
2
S Serializers are disabled. Only the clocks are enabled and output for external
receivers and/or transmitters.
In Slave mode, the I
2
S receives the Serial Clock and the Word Select/Frame Sync Signal from an
external master. SCKn and FSn pins are inputs.
29.6.4 I
2
S Format - Reception and Transmission Sequence with Word Select
As specified in the I
2
S protocol, data bits are left-adjusted in the Word Select slot, with the MSB
transmitted first, starting one clock period after the transition on the Word Select line.
Figure 29-5. I
2
S Reception and Transmission Sequence
SAM D21 Family
I2S - Inter-IC Sound Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 635