Datasheet

In Controller mode, only the Clock generation unit needs to be configured by writing to the CTRLA and
CLKCTRLn registers, where parameters such as clock division factors, Number of slots, Slot size, Frame
Sync signal, clock enable are selected.
29.6.2.1.3 MCKn Clock Frequency
When the I
2
S is in Master mode, writing a '1' to CLKCTRLn.MCKEN will output GCLK_I2S_n as Master
Clock to the MCKn pin. The Master Clock to MCKn pin can be divided by writing to CLKCTRLn.MCKSEL
and CLKCTRLn.MCKOUTDIV. The Master Clock (MCKn) frequency is GCLK_I2S_n frequency divided by
(MCLKOUTDIV+1).
 MCKn =
 GCLK_2_
MCKOUTDIV+1
29.6.2.1.4 SCKn Clock Frequency
When the Serial Clock (SCKn) is generated from GCLK_I2S_n and both CLKCTRLn.MCKSEL and
CLKCTRLn.SCKSEL are zero, the Serial Clock (SCKn) frequency is GCLK_I2S_n frequency divided by
(MCKDIV+1).
i.e.
 CKn =
 GCLK_2_
MCKDIV+1
29.6.2.1.5 Relation Between MCKn, SCKn, and Sampling Frequency fs
Based on sampling frequency fs, the SCKn frequency requirement can be calculated:
•
SCKn frequency:

SCKn
=  × total_number_of_bits_per_frame
,
• Where total_number_of_bits_per_frame = number_of_slots × number_of_bits_per_slots.
• The number of slots is selected by writing to the Number of Slots in Frame bit field in the Clock Unit
n Control (CLKCTRLn) register: number_of_slots = NBSLOTS + 1.
• The number of bits per slot (8, 16, 24, or 32 bit) is selected by writing to the Slot Size bit field in
CLKCTRLn: .
• Consequently,

SCKn
= 8 ×  × NBSLOTS + 1 × SLOTSIZE + 1
.
The clock frequencies 
SCKn
and 
MCKn
are derived from the generic clock frequency 
GCLK_I2S_n
:
•

GCLK_I2S_n
= 
SCKn
× CLKCTRLn.MCKDIV + 1
= 8 ×  × NBSLOTS + 1 × SLOTSIZE + 1 × MCKDIV + 1
, and
•

GCLK_I2S_n
= 
MCKn
× MCKOUTDIV + 1
.
Substituting the right hand sides of the two last equations yields:

MCKn
=

GCLK_I2S_n
MCKOUTDIV+1

MCKn
=
8  SLOTSIZE+1  NBSLOTS+1  MCKDIV+1
MCKOUTDIV+1
If a Master Clock output is not required, the GCLK_I2S generic clock can be configured as SCKn by
writing a '0'to CLKCTRLn.MCKDIV. Alternatively, if the frequency of the generic clock is a multiple of the
required SCKn frequency, the MCKn-to-SCKn divider can be used with the ratio defined by writing the
CLKCTRLn.MCKDIV field.
SAM D21 Family
I2S - Inter-IC Sound Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 634