Datasheet

Figure 29-4. I
2
S Clocks Generation
29.6.2.1.1 Slave Mode
In Slave mode, the Serial Clock and Frame Sync (Word Select in I
2
S mode and Frame Sync in TDM
mode) are driven by an external master. SCKn and FSn pins are inputs and no generic clock is required
by the I
2
S.
29.6.2.1.2 Master Mode and Controller Mode
In Master Mode, the Master Clock (MCKn), the Serial Clock (SCKn), and the Frame Sync Clock (FSn) are
generated by the I
2
S controller. The user can configure the Master Clock, Serial Clock, and Word Select
Frame Sync signal (Word Select in I
2
S mode and Frame Sync in TDM mode) using the Clock Unit n
Control register (CLKCTRLn). MCKn, SCKn, and FSn pins are outputs and a generic clock is used to
derive the I
2
S clocks.
In some applications, audio CODECs connected to the I
2
S pins may require a Master Clock signal with a
frequency multiple of the audio sample frequency fs, such as 256×fs.
SAM D21 Family
I2S - Inter-IC Sound Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 633