Datasheet

f
SCKn
= 48kHz × 6 × 32 = 9.216MHz
This frequency can be achieved by dividing the I
2
S generic clock output of 18.432MHz by
factor 2: Writing CLKCTRLn.MCKDIV=0x1 will select the correct division factor and
output the desired SCKn frequency of 9.216MHz to the SCKn pin.
If MCKn is not required, the generic clock could be set to 9.216MHz and
CLKCTRLn.MCKDIV=0x0.
29.6.2 Basic Operation
The Receiver can be operated by reading the Data Holding register (DATAm), whenever the Receive
Ready m bit in the Interrupt Flag Status and Clear register (INTFLAG.RXRDYm) is set. Successive
values read from DATAm register will correspond to the samples from the left and right audio channels. In
TDM mode, the successive values read from DATAm register correspond to the first slot to the last slot.
For instance, if I
2
S is configured in TDM mode with 4 slots in a frame, then successive values written to
DATAm register correspond to first, second, third, and fourth slot. The number of slots in TDM is
configured in CLKCTRLn.NBSLOTS.
The Transmitter can be operated by writing to the Data Holding register (DATAm), whenever the Transmit
Ready m bit in the Interrupt Flag Status and Clear register (INTFLAG.TXRDYm) is set. Successive values
written to DATAm register should correspond to the samples from the left and right audio channels. In
TDM mode, the successive values written to DATAm register correspond to the first, second, third, slot to
the last slot. The number of slots in TDM is configured in CLKCTRLn.NBSLOTS.
The Receive Ready and Transmit Ready bits can be polled by reading the INTFLAG register.
The processor load can be reduced by enabling interrupt-driven operation. The RXRDYm and/or
TXRDYm interrupt requests can be enabled by writing a '1' to the corresponding bit in the Interrupt
Enable register (INTENSET). The interrupt service routine associated to the I
2
S interrupt request will then
be executed whenever Receive Ready or Transmit Ready status bits are set.
The processor load can be reduced further by enabling DMA-driven operation. Then, the DMA channels
support up to four trigger sources from the I
2
S peripheral. These four trigger sources in DMAC channel
are
• I2S RX 0,
• I2S RX 1,
• I2S TX 0, and
• I2S TX 1.
For further reference, these are called I2S_DMAC_ID_RX_m and I2S_DMAC_ID_TX_m triggers
(m=0..1). By using these trigger sources, one DMA data transfer will be executed whenever the Receive
Ready or Transmit Ready status bits are set.
29.6.2.1 Master Clock, Serial Clock, and Frame Sync Generation
The generation of clocks in the I
2
S is described in the next figure.
SAM D21 Family
I2S - Inter-IC Sound Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 632