Datasheet
Write-protection does not apply for accesses through an external debugger.
29.5.9 Analog Connections
Not applicable.
29.6 Functional Description
29.6.1 Principle of Operation
The I
2
S uses three or four communication lines for synchronous data transfer:
• SDm for receiving or transmitting in Serializer m (m=0..1)
• SCKn for the serial clock in Clock Unit n (n=0..1)
• FSn for the frame synchronization or I
2
S word select, identifying the beginning of each frame
• Optionally, MCKn to output an oversampling clock to an external codec
I
2
S data transfer is frame based, where a serial frame:
• Starts with the frame synchronization active edge, and
• Consists of 1 to 8 data slots, that are 8-, 16-, 24-, or 32-bit wide.
Each data slot is used to transfer one data sample of 8, 16, 18, 20, 24 or 32 bits.
Frame based data transfer is described in the following figure:
Figure 29-2. Data Format: Frames, Slot, Bits and Clocks
I
2
S supports multiple data formats such as:
• 32-, 24-, 20-, 18-, 16-, and 8-bit mono or stereo format
• 16- and 8-bit compact stereo format, with left and right samples packed in the same word to reduce
data transfers
SAM D21 Family
I2S - Inter-IC Sound Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 629