Datasheet

29.5.2 Power Management
The I
2
S will continue to operate in any sleep mode where the selected source clocks are running.
29.5.3 Clocks
The clock for the I
2
S bus interface (CLK_I2S_APB) is generated by the Power Manager. This clock is
disabled at reset, and can be enabled in the Power Manager. It is recommended to disable the I
2
S before
disabling the clock, to avoid freezing the I
2
S in an undefined state.
There are two generic clocks, GCLK_I2S_0 and GCLK_I2S_1, connected to the I
2
S peripheral, one for
each I
2
S clock unit. The generic clocks (GCLK_I2S_n, n=0..1) can be set to a wide range of frequencies
and clock sources. The GCLK_I2S_n must be enabled and configured before use.
The GCLK_I2S_n clocks must be enabled and configured before triggering Software Reset, so that the
logic in all clock domains can be reset.
The generic clocks are only used in Master mode and Controller mode. In Master mode, the clock from a
single clock unit can be used for both Serializers to handle synchronous transfers, or a separate clock
from different clock units can be used for each Serializer to handle transfers on non-related clocks.
Related Links
15. GCLK - Generic Clock Controller
29.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). Using the I
2
S DMA requests
requires the DMA Controller to be configured first.
Related Links
20. DMAC – Direct Memory Access Controller
29.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using I
2
S interrupts requires the
interrupt controller to be configured first.
Related Links
11.2 Nested Vector Interrupt Controller
29.5.6 Events
Not applicable.
29.5.7 Debug Operation
When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is
configured to require periodical service by the CPU through interrupts or similar, improper operation or
data loss may result during debugging. This peripheral can be forced to halt operation during debugging.
29.5.8 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC),
except for the following:
• DATAm
• INTFLAG
• SYNCBUSY
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
SAM D21 Family
I2S - Inter-IC Sound Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 628