Datasheet

– Suitable for a wide range of sample frequencies fs, including 32kHz, 44.1kHz, 48kHz,

88.2kHz, 96kHz, and 192kHz

– 16×fs to 1024×fs Master Clock generated for external audio CODECs

• Master, slave, and controller modes:

– Master: Data received/transmitted based on internally-generated clocks. Output Serial Clock

on SCKn pin, Master Clock on MCKn pin, and Frame Sync Clock on FSn pin

– Slave: Data received/transmitted based on external clocks on Serial Clock pin (SCKn) or

Master Clock pin (MCKn)

– Controller: Only output internally generated Master clock (MCKn), Serial Clock (SCKn), and

Frame Sync Clock (FSn)

• Individual enabling and disabling of Clock Units and Serializers

• DMA interfaces for each Serializer receiver or transmitter to reduce processor overhead:

– Either one DMA channel for all data slots or

– One DMA channel per data channel in stereo

• Smart Data Holding register management to avoid data slots mix after overrun or underrun

29.3 Block Diagram

Figure 29-1. I

S Block Diagram

SAM D21 Family

I2S - Inter-IC Sound Controller

Datasheet Complete

DS40001882D-page 626