Datasheet

28.10.10 Data
Name:  DATA
Offset:  0x28
Reset:  0x0000
Property:  -
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – DATA[7:0] Data
The master data register I/O location (DATA) provides access to the master transmit and receive data
buffers. Reading valid data or writing data to be transmitted can be successfully done only when SCL is
held low by the master (STATUS.CLKHOLD is set). An exception is reading the last data byte after the
stop condition has been sent.
Accessing DATA.DATA auto-triggers I
2
C bus operations. The operation performed depends on the state
of CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write).
Writing or reading DATA.DATA when not in Smart mode does not require synchronization.
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 621