Datasheet

28.10.8 Synchronization Busy
Name: SYNCBUSY
Offset: 0x1C
Reset: 0x00000000
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
SYSOP ENABLE SWRST
Access
R R R
Reset 0 0 0
Bit 2 – SYSOP System Operation Synchronization Busy
Writing CTRLB.CMD, STATUS.BUSSTATE, ADDR, or DATA when the SERCOM is enabled requires
synchronization. When written, the SYNCBUSY.SYSOP bit will be set until synchronization is complete.
Writing CTRLB.CMD or CTRLB.FIFOCLR, STATUS.BUSSTATE, ADDR, or DATA when the SERCOM is
enabled requires synchronization. When written, the SYNCBUSY.SYSOP bit will be set until
synchronization is complete.
Value Description
0
System operation synchronization is not busy.
1
System operation synchronization is busy.
Bit 1 – ENABLE SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the
SYNCBUSY.ENABLE bit will be set until synchronization is complete.
Value Description
0
Enable synchronization is not busy.
1
Enable synchronization is busy.
Bit 0 – SWRST Software Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the
SYNCBUSY.SWRST bit will be set until synchronization is complete.
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 617