Datasheet

Bit 0 – BUSERR Bus Error

This bit indicates that an illegal bus condition has occurred on the bus, regardless of bus ownership. An

illegal bus condition is detected if a protocol violating start, repeated start or stop is detected on the I

bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If a

time-out occurs during a frame, this is also considered a protocol violation, and will set BUSERR.

If the I

C master is the bus owner at the time a bus error occurs, STATUS.ARBLOST and INTFLAG.MB

will be set in addition to BUSERR.

Writing the ADDR.ADDR register will automatically clear the BUSERR flag.

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear it.

This bit is not write-synchronized.

SAM D21 Family

SERCOM I2C – Inter-Integrated Circuit

Datasheet Complete

DS40001882D-page 616