Datasheet

This bit is cleared when the corresponding interrupt flag is cleared and the next operation is given.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
This bit is not write-synchronized.
Bit 6 – LOWTOUT SCL Low Time-Out
This bit is set if an SCL low time-out occurs.
Writing '1' to this bit location will clear this bit. This flag is automatically cleared when writing to the ADDR
register.
Writing '0' to this bit has no effect.
This bit is not write-synchronized.
Bits 5:4 – BUSSTATE[1:0] Bus State
These bits indicate the current I
2
C bus state.
When in UNKNOWN state, writing 0x1 to BUSSTATE forces the bus state into the IDLE state. The bus
state cannot be forced into any other state.
Writing BUSSTATE to idle will set SYNCBUSY.SYSOP.
Value Name Description
0x0
UNKNOWN The bus state is unknown to the I
2
C master and will wait for a stop condition to
be detected or wait to be forced into an idle state by software
0x1
IDLE The bus state is waiting for a transaction to be initialized
0x2
OWNER The I
2
C master is the current owner of the bus
0x3
BUSY Some other I
2
C master owns the bus
Bit 2 – RXNACK Received Not Acknowledge
This bit indicates whether the last address or data packet sent was acknowledged or not.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
This bit is not write-synchronized.
Value Description
0
Slave responded with ACK.
1
Slave responded with NACK.
Bit 1 – ARBLOST Arbitration Lost
This bit is set if arbitration is lost while transmitting a high data bit or a NACK bit, or while issuing a start or
repeated start condition on the bus. The Master on Bus interrupt flag (INTFLAG.MB) will be set when
STATUS.ARBLOST is set.
Writing the ADDR.ADDR register will automatically clear STATUS.ARBLOST.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
This bit is not write-synchronized.
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 615