Datasheet

28.10.7 Status
Name: STATUS
Offset: 0x1A
Reset: 0x0000
Property: Write-Synchronized
Bit 15 14 13 12 11 10 9 8
LENERR SEXTTOUT MEXTTOUT
Access
R/W R/W R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
CLKHOLD LOWTOUT BUSSTATE[1:0] RXNACK ARBLOST BUSERR
Access
R R/W R/W R/W R R/W R/W
Reset 0 0 0 0 0 0 0
Bit 10 – LENERR Transaction Length Error
This bit is set when automatic length is used for a DMA transaction and the slave sends a NACK before
ADDR.LEN bytes have been written by the master.
Writing '1' to this bit location will clear STATUS.LENERR. This flag is automatically cleared when writing
to the ADDR register.
Writing '0' to this bit has no effect.
This bit is not write-synchronized.
Bit 9 – SEXTTOUT Slave SCL Low Extend Time-Out
This bit is set if a slave SCL low extend time-out occurs.
This bit is automatically cleared when writing to the ADDR register.
Writing '1' to this bit location will clear SEXTTOUT. Normal use of the I
2
C interface does not require the
SEXTTOUT flag to be cleared by this method.
Writing '0' to this bit has no effect.
This bit is not write-synchronized.
Bit 8 – MEXTTOUT Master SCL Low Extend Time-Out
This bit is set if a master SCL low time-out occurs.
Writing '1' to this bit location will clear STATUS.MEXTTOUT. This flag is automatically cleared when
writing to the ADDR register.
Writing '0' to this bit has no effect.
This bit is not write-synchronized.
Bit 7 – CLKHOLD Clock Hold
This bit is set when the master is holding the SCL line low, stretching the I
2
C clock. Software should
consider this bit when INTFLAG.SB or INTFLAG.MB is set.
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 614