Datasheet

28.10.4 Interrupt Enable Clear
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 7 6 5 4 3 2 1 0
ERROR RXFF TXFE SB MB
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 – ERROR Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 4 – RXFF RX FIFO Full Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the RX FIFO Full bit, which disables the RX FIFO Full interrupt.
Value Description
0
The RX FIFO Full interrupt is disabled.
1
The RX FIFO Full interrupt is enabled.
Bit 3 – TXFE TX FIFO Empty Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the TX FIFO Empty bit, which disables the TX FIFO Empty interrupt.
Value Description
0
The TX FIFO Empty interrupt is disabled.
1
The TX FIFO Empty interrupt is enabled.
Bit 1 – SB Slave on Bus Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Slave on Bus Interrupt Enable bit, which disables the Slave on Bus
interrupt.
Value Description
0
The Slave on Bus interrupt is disabled.
1
The Slave on Bus interrupt is enabled.
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 608