Datasheet

Value Description
0
Send ACK.
1
Send NACK.
Bits 17:16 – CMD[1:0] Command
Writing these bits triggers a master operation as described below. The CMD bits are strobe bits, and
always read as zero. The acknowledge action is only valid in master read mode. In master write mode, a
command will only result in a repeated start or stop condition. The CTRLB.ACKACT bit and the CMD bits
can be written at the same time, and then the acknowledge action will be updated before the command is
triggered.
Commands can only be issued when either the Slave on Bus interrupt flag (INTFLAG.SB) or Master on
Bus interrupt flag (INTFLAG.MB) is '1'.
If CMD 0x1 is issued, a repeated start will be issued followed by the transmission of the current address
in ADDR.ADDR. If another address is desired, ADDR.ADDR must be written instead of the CMD bits.
This will trigger a repeated start followed by transmission of the new address.
Issuing a command will set the System Operation bit in the Synchronization Busy register
(SYNCBUSY.SYSOP).
Table 28-8. Command Description
CMD[1:0] Direction Action
0x0 X (No action)
0x1 X Execute acknowledge action succeeded by repeated Start
0x2 0 (Write) No operation
1 (Read) Execute acknowledge action succeeded by a byte read operation
0x3 X Execute acknowledge action succeeded by issuing a stop condition
These bits are not enable-protected.
Bit 9 – QCEN Quick Command Enable
This bit is not write-synchronized.
Value Description
0
Quick Command is disabled.
1
Quick Command is enabled.
Bit 8 – SMEN Smart Mode Enable
When smart mode is enabled, acknowledge action is sent when DATA.DATA is read.
This bit is not write-synchronized.
Value Description
0
Smart mode is disabled.
1
Smart mode is enabled.
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 605