Datasheet

28.10.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
FIFOCLR[1:0] ACKACT CMD[1:0]
Access
R/W R/W R/W W W
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
QCEN SMEN
Access
R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
Access
Reset
Bits 23:22 – FIFOCLR[1:0] FIFO Clear
When these bits are set, the corresponding FIFO will be cleared. The bits will automatically clear when
SYNCBUSY.SYSOP = 0.
These bits are not enable-protected.
FIFOCLR[1:0] Name Description
0x0 NONE No action
0x1 TXFIFO Clear TX FIFO
0x2 RXFIFO Clear RX FIFO
0x3 BOTH Clear both TX/RX FIFO
Bit 18 – ACKACT Acknowledge Action
This bit defines the I
2
C master's acknowledge behavior after a data byte is received from the I
2
C slave.
The acknowledge action is executed when a command is written to CTRLB.CMD, or if smart mode is
enabled (CTRLB.SMEN is written to one), when DATA.DATA is read.
This bit is not enable-protected.
This bit is not write-synchronized.
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 604