Datasheet

Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same

write-operation will be discarded. Any register write access during the ongoing reset will result in an APB

error. Reading any register will return the reset value of the register.

Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete.

CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.

This bit is not enable-protected.

Value Description

There is no reset operation ongoing.

The reset operation is ongoing.

SAM D21 Family

SERCOM I2C – Inter-Integrated Circuit

Datasheet Complete

DS40001882D-page 603