Datasheet

Bits 21:20 – SDAHOLD[1:0] SDA Hold Time
These bits define the SDA hold time with respect to the negative edge of SCL.
These bits are not synchronized.
Value Name Description
0x0
DIS Disabled
0x1
75NS 50-100ns hold time
0x2
450NS 300-600ns hold time
0x3
600NS 400-800ns hold time
Bit 16 – PINOUT Pin Usage
This bit set the pin usage to either two- or four-wire operation:
This bit is not synchronized.
Value Description
0
4-wire operation disabled.
1
4-wire operation enabled.
Bit 7 – RUNSTDBY Run in Standby
This bit defines the functionality in standby sleep mode.
This bit is not synchronized.
Value Description
0
GCLK_SERCOMx_CORE is disabled and the I
2
C master will not operate in standby sleep
mode.
1
GCLK_SERCOMx_CORE is enabled in all sleep modes.
Bits 4:2 – MODE[2:0] Operating Mode
These bits must be written to 0x5 to select the I
2
C master serial communication interface of the
SERCOM.
These bits are not synchronized.
Bit 1 – ENABLE Enable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable
Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE
will be cleared when the operation is complete.
This bit is not enable-protected.
Value Description
0
The peripheral is disabled or being disabled.
1
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the
SERCOM will be disabled.
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 602