Datasheet

Value Name Description
0x0
DIS Disabled
0x1
55US 5-6 SCL cycle time-out (50-60µs)
0x2
105US 10-11 SCL cycle time-out (100-110µs)
0x3
205US 20-21 SCL cycle time-out (200-210µs)
Bit 27 – SCLSM SCL Clock Stretch Mode
This bit controls when SCL will be stretched for software interaction.
This bit is not synchronized.
Value Description
0
SCL stretch according to Figure 28-5.
1
SCL stretch only after ACK bit, Figure 28-6.
Bits 25:24 – SPEED[1:0] Transfer Speed
These bits define bus speed.
These bits are not synchronized.
Value Description
0x0
Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz
0x1
Fast-mode Plus (Fm+) up to 1 MHz
0x2
High-speed mode (Hs-mode) up to 3.4 MHz
0x3
Reserved
Bit 23 – SEXTTOEN Slave SCL Low Extend Time-Out
This bit enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms
from the initial START to a STOP, the master will release its clock hold if enabled, and complete the
current transaction. A STOP will automatically be transmitted.
SB or MB will be set as normal, but CLKHOLD will be release. The MEXTTOUT and BUSERR status bits
will be set.
This bit is not synchronized.
Value Description
0
Time-out disabled
1
Time-out enabled
Bit 22 – MEXTTOEN Master SCL Low Extend Time-Out
This bit enables the master SCL low extend time-out. If SCL is cumulatively held low for greater than
10ms from START-to-ACK, ACK-to-ACK, or ACK-to-STOP the master will release its clock hold if
enabled, and complete the current transaction. A STOP will automatically be transmitted.
SB or MB will be set as normal, but CLKHOLD will be released. The MEXTTOUT and BUSERR status
bits will be set.
This bit is not synchronized.
Value Description
0
Time-out disabled
1
Time-out enabled
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 601