Datasheet

28.8.9 Data

Name: DATA

Offset: 0x28

Reset: 0x0000

Property: Write-Synchronized, Read-Synchronized

Bit 15 14 13 12 11 10 9 8

Access

Reset

Bit 7 6 5 4 3 2 1 0

DATA[7:0]

Access

R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – DATA[7:0] Data

The slave data register I/O location (DATA.DATA) provides access to the master transmit and receive

data buffers. Reading valid data or writing data to be transmitted can be successfully done only when

SCL is held low by the slave (STATUS.CLKHOLD is set). An exception occurs when reading the last data

byte after the stop condition has been received.

Accessing DATA.DATA auto-triggers I

C bus operations. The operation performed depends on the state

of CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write).

Writing or reading DATA.DATA when not in smart mode does not require synchronization.

SAM D21 Family

SERCOM I2C – Inter-Integrated Circuit

Datasheet Complete

DS40001882D-page 595