Datasheet

The flag is cleared by hardware when CTRL.CMD is written.

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Address Match interrupt flag. When cleared, an ACK/NACK will be sent

according to CTRLB.ACKACT.

Bit 0 – PREC Stop Received

This flag is set when a stop condition is detected for a transaction being processed. A stop condition

detected between a bus master and another slave will not set this flag, unless the PMBus Group

Command is enabled in the Control B register (CTRLB.GCMD=1).

This flag is cleared by hardware after a command is issued on the next address match.

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Stop Received interrupt flag.

SAM D21 Family

SERCOM I2C – Inter-Integrated Circuit

Datasheet Complete

DS40001882D-page 588