Datasheet

Value Description
0x0
Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz
0x1
Fast-mode Plus (Fm+) up to 1 MHz
0x2
High-speed mode (Hs-mode) up to 3.4 MHz
0x3
Reserved
Bit 23 – SEXTTOEN Slave SCL Low Extend Time-Out
This bit enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms
from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal
state machine. Any interrupt flags set at the time of time-out will remain set. If the address was
recognized, PREC will be set when a STOP is received.
This bit is not synchronized.
Value Description
0
Time-out disabled
1
Time-out enabled
Bits 21:20 – SDAHOLD[1:0] SDA Hold Time
These bits define the SDA hold time with respect to the negative edge of SCL.
These bits are not synchronized.
Value Name Description
0x0
DIS Disabled
0x1
75 50-100ns hold time
0x2
450 300-600ns hold time
0x3
600 400-800ns hold time
Bit 16 – PINOUT Pin Usage
This bit sets the pin usage to either two- or four-wire operation:
This bit is not synchronized.
Value Description
0
4-wire operation disabled
1
4-wire operation enabled
Bit 7 – RUNSTDBY Run in Standby
This bit defines the functionality in standby sleep mode.
This bit is not synchronized.
Value Description
0
Disabled – All reception is dropped.
1
Wake on address match, if enabled.
Bits 4:2 – MODE[2:0] Operating Mode
These bits must be written to 0x04 to select the I
2
C slave serial communication interface of the SERCOM.
These bits are not synchronized.
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 578