Datasheet

28.6.4.3 Events

Not applicable.

28.6.5 Sleep Mode Operation

C Master Operation

The generic clock (GCLK_SERCOMx_CORE) will continue to run in idle sleep mode. If the Run In

Standby bit in the Control A register (CTRLA.RUNSTDBY) is '1', the GLK_SERCOMx_CORE will also run

in standby sleep mode. Any interrupt can wake up the device.

If CTRLA.RUNSTDBY=0, the GLK_SERCOMx_CORE will be disabled after any ongoing transaction is

finished. Any interrupt can wake up the device.

C Slave Operation

Writing CTRLA.RUNSTDBY=1 will allow the Address Match interrupt to wake up the device.

When CTRLA.RUNSTDBY=0, all receptions will be dropped.

28.6.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers

need to be synchronized when written or read.

The following bits are synchronized when written:

• Software Reset bit in the CTRLA register (CTRLA.SWRST)

• Enable bit in the CTRLA register (CTRLA.ENABLE)

• Command bits in CTRLB register (CTRLB.CMD)

• FIFO Clear bits in CTRLB register (CTRLB.FIFOCLR)

• Write to Bus State bits in the Status register (STATUS.BUSSTATE)

• Address bits in the Address register (ADDR.ADDR) when in master operation.

The following registers are synchronized when written:

• Data (DATA) when in master operation

Required write-synchronization is denoted by the "Write-Synchronized" property in the register

description.