Datasheet

ManualsBrandsMicrochip ManualsARM MicrocontrollersARM® Cortex® M0+ SAM Microcontroller 32bit 256KB TQFP

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If a NACK is received by the slave for a master write transaction before ADDR.LEN bytes, a STOP will be

automatically generated and the length error (STATUS.LENERR) will be raised along with the

INTFLAG.ERROR interrupt.

The I

C master generates the following requests:

• Read data received (RX): The request is set when master read data is received. The request is

cleared when DATA is read.

• Write data needed for transmit (TX): The request is set when data is needed for a master write

operation. The request is cleared when DATA is written.

• Read data received (RX): If the FIFO is disabled, the request is set when master read data is

received. If the FIFO is enabled, the request is set when the RX FIFO threshold is reached. The

request is cleared when DATA is read.

• Write data needed for transmit (TX): If the FIFO is disabled, the request is set when data is needed

for a master write operation. If the FIFO is enabled, the request is set when the TX FIFO threshold

is reached (CTRLC.TXTRHOLD). The request is cleared when DATA is written.

28.6.4.2 Interrupts

The I

C slave has the following interrupt sources. These are asynchronous interrupts. They can wake-up

the device from any sleep mode:

• Error (ERROR)

• RX FIFO Full (RXFF)

• TX FIFO Empty (TXFE)

• Data Ready (DRDY)

• Address Match (AMATCH)

• Stop Received (PREC)

The I

C master has the following interrupt sources. These are asynchronous interrupts. They can wake-

up the device from any sleep mode:

• Error (ERROR)

• RX FIFO Full (RXFF)

• TX FIFO Empty (TXFE)

• Slave on Bus (SB)

• Master on Bus (MB)

Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear

enabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and

disabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An

interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.

The interrupt request active until the interrupt flag is cleared, the interrupt is disabled or the I

C is reset.

See the INTFLAG register for details on how to clear interrupt flags.

The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally

enabled for interrupt requests. Refer to Nested Vector Interrupt Controller for details.