Datasheet
Table 28-6. Module Request for SERCOM I
2
C Master
Condition Request
DMA Interrupt Event
Data needed for transmit (TX)
(Master transmit mode)
Yes
(request cleared
when data is
written)
NA
Data needed for transmit (RX)
(Master transmit mode)
Yes
(request cleared
when data is
read)
Master on Bus (MB) Yes
Stop received (SB) Yes
TX FIFO Empty (TXFE) Yes
RX FIFO Full (RXFF) Yes
Error (ERROR) Yes
28.6.4.1 DMA Operation
Smart mode must be enabled for DMA operation in the Control B register by writing CTRLB.SMEN=1.
28.6.4.1.1 Slave DMA
When using the I
2
C slave with DMA, an address match will cause the address interrupt flag
(INTFLAG.ADDRMATCH) to be raised. After the interrupt has been serviced, data transfer will be
performed through DMA.
The I
2
C slave generates the following requests:
• Write data received (RX): The request is set when master write data is received. The request is
cleared when DATA is read.
• Read data needed for transmit (TX): The request is set when data is needed for a master read
operation. The request is cleared when DATA is written.
• Write data received (RX): If the FIFO is disabled, the request is set when master write data is
received. If the FIFO is enabled, the request is set when the RX FIFO threshold is reached
(CTRLC.RXTRHOLD). The request is cleared when DATA is read.
• Read data needed for transmit (TX): If the FIFO is disabled, the request is set when data is needed
for a master read operation. If the FIFO is enabled, the request is set when the TX FIFO threshold
is reached (CTRLC.TXTRHOLD). The request is cleared when DATA is written.
28.6.4.1.2 Master DMA
When using the I
2
C master with DMA, the ADDR register must be written with the desired address
(ADDR.ADDR), transaction length (ADDR.LEN), and transaction length enable (ADDR.LENEN). When
ADDR.LENEN is written to 1 along with ADDR.ADDR, ADDR.LEN determines the number of data bytes
in the transaction from 0 to 255. DMA is then used to transfer ADDR.LEN bytes followed by an
automatically generated NACK (for master reads) and a STOP.
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 572