Datasheet

28.6.4 DMA, Interrupts and Events
This chapter provides DMA and interrupt conditions when the optional FIFO is disabled. For details when
the FIFO is enabled, refer to FIFO Support.
Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) will be set when the interrupt condition is meet. Each interrupt can be individually
enabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and
disabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An
interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request is active until the interrupt flag is cleared, the interrupt is disabled or the I
2
C is reset.
See the 28.8.5 INTFLAG (Slave) or 28.10.6 INTFLAG (Master) register for details on how to clear
interrupt flags.
Table 28-5. Module Request for SERCOM I
2
C Slave
Condition Request
DMA Interrupt Event
Data needed for transmit (TX)
(Slave transmit mode)
Yes
(request cleared
when data is
written)
NA
Data received (RX) (Slave receive
mode)
Yes
(request cleared
when data is
read)
Data Ready (DRDY) Yes
Address Match (AMATCH) Yes
Stop received (PREC) Yes
TX FIFO Empty (TXFE) Yes
RX FIFO Full (RXFF) Yes
Error (ERROR) Yes
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 571