Datasheet

When using the I2C configured as Master, the Address register must be written with the desired address
(ADDR.ADDR), and optionally, the transaction Length and transaction Length Enable bits (ADDR.LEN
and ADDR.LENEN) can be written if the 32-bit extension is enabled (CTRLC.DATA32B).
In slave operation, the Address Match interrupt in the Interrupt Flag Status and Clear register
(INTFLAG.AMATCH) is set after the address is received and and the SCL clock is stretched as long as
the address is not read from the FIFO. When the address is read, the FIFO pointers are cleared in
preparation for the incomming frame.
The FIFO threshold settings allow (CTRLC.TXTRHOLD, CTRLC.RXTRHOLD) allow flexible interrupt,
DMA trigger and bus condition generations, as described bellow.
The FIFO is fully accessible if the SERCOM is halted, by writting the corresponding CPU FIFO pointer in
the FIFOPTR register. The RX or TX FIFO can be individually cleared, by setting the respective FIFO
Clear bit in the Control B register (CTRLB.FIFOCLR). The FIFO Clear must be written before data
transfer begins. Writing the FIFO Clear bits while a frame is in progress will produce unpredicatable
results.
28.6.3.5.1 Hardware Actions in Master Mode
Table 28-1. Interrupts Request Conditions for Valid SERCOM I
2
C Master Configurations
Direction
CTRLB.
SMEN
CTRLC.
DATA32B
LENGTH.
LENEN
Action
Master Write 0 0 0 • INTFLAG.TXFE = 1 if TX FIFO is empty
• INTFLAG.TXFE = 1 if TX FIFO threshold reached
• INTFLAG.MB = 1 if TX FIFO is empty and SCL
hold
0 1 0
0 1 1 • INTFLAG.TXFE = 1 if TX FIFO is empty or length
transaction is completed
• INTFLAG.TXFE = 1 if TX FIFO threshold is
reached and length transaction is not completed
• INTFLAG.MB = 1 if TX FIFO is empty and SCL
hold, or length transaction is completed
1 0 0 • INTFLAG.TXFE = 1 if TX FIFO is empty
• INTFLAG.TXFE = 1 if TX FIFO threshold reached
• INTFLAG.MB = 1 if TX FIFO is empty and SCL
hold
1 1 0
1 1 1
Master Read 0 0 0 • INTFLAG.SB = 1 if RX FIFO is full
• INTFLAG.RXFE = 1 if RX FIFO threshold reached
0 1 0
0 1 1
1 0 0
1 1 0
1 1 1
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 567