Datasheet

Figure 28-14. I
2
C Pad Interface
SCL/SDA
pad
I2C
Driver
SCL_OUT/
SDA_OUT
pad
PINOUT
PINOUT
SCL_IN/
SDA_IN
SCL_OUT/
SDA_OUT
28.6.3.4 Quick Command
Setting the Quick Command Enable bit in the Control B register (CTRLB.QCEN) enables quick command.
When quick command is enabled, the corresponding interrupt flag (INTFLAG.SB or INTFLAG.MB) is set
immediately after the slave acknowledges the address. At this point, the software can either issue a stop
command or a repeated start by writing CTRLB.CMD or ADDR.ADDR.
28.6.3.5 FIFO Operation
For better system bus utilization, the I2C embeds up to 16-bytes FIFO capability. The receive / transmit
buffer is considered to have the FIFO mode enabled when the FIFOEN bit in CTRLC register is set
(CTRLC.FIFOEN = 1). By default, the FIFO can act as a 16-by-8-bit array, or as a 4-by-32-bit array,
depending on the setting of the CTRLC.DATA32B bit.
The hardware around this array implements four pointers, called the CPU Write Pointer (CPUWRPTR),
the CPU Read Pointer (CPURDPTR), the I2C Write pointer (I2CWRPTR) and the I2C Read pointer
(I2CRDPTR). All of these pointers reset to ‘0’. The CPUWRPTR and CPURDPTR pointers are native to
the CPU clock domain, while the I2CWRPTR and I2CRDPTR are native to the I2C domain. The location
pointed to by the CPUWRPTR is the current TX FIFO. The location pointed to by the CPURDPTR
becomes the current RX FIFO. Writes to DATA register by the CPU will point to TX FIFO. Reads to DATA
register by the CPU will point to RX FIFO. The location pointed to by the I2CWRPTR / I2CRDPTR is
logically the current shift register.
Figure 28-15. FIFO Overview
RX FIFO
TX FIFO
DATA DATA
Shift Register
CPUWRPTR
CPURDPTR
I2CWRPTR
I2CRDPTR
TX FIFO
THRESHOLD
Interrupt /
DMA Req.
Interrupt /
DMA Req.
RX FIFO
THRESHOLD
0 SDA
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 566