Datasheet

Figure 28-13. PMBus Group Command Example
A
S
A
n Bytes
W
ADDRESS 0
Command/Data
A
Sr
A
n Bytes
W
ADDRESS 1
(this slave)
Command/Data
S
W
S
W
A
Sr
A
n Bytes
W
ADDRESS 2
Command/Data
P
S
W
AMATCH INTERRUPT DRDY INTERRUPT
PREC INTERRUPT
28.6.3 Additional Features
28.6.3.1 SMBus
The I
2
C includes three hardware SCL low time-outs which allow a time-out to occur for SMBus SCL low
time-out, master extend time-out, and slave extend time-out. This allows for SMBus functionality These
time-outs are driven by the GCLK_SERCOM_SLOW clock. The GCLK_SERCOM_SLOW clock is used to
accurately time the time-out and must be configured to use a 32KHz oscillator. The I
2
C interface also
allows for a SMBus compatible SDA hold time.
• T
TIMEOUT
: SCL low time of 25..35ms – Measured for a single SCL low period. It is enabled by
CTRLA.LOWTOUTEN.
• T
LOW:SEXT
: Cumulative clock low extend time of 25 ms – Measured as the cumulative SCL low
extend time by a slave device in a single message from the initial START to the STOP. It is enabled
by CTRLA.SEXTTOEN.
• T
LOW:MEXT
: Cumulative clock low extend time of 10 ms – Measured as the cumulative SCL low
extend time by the master device within a single byte from START-to-ACK, ACK-to-ACK, or ACK-
to-STOP. It is enabled by CTRLA.MEXTTOEN.
28.6.3.2 Smart Mode
The I
2
C interface has a smart mode that simplifies application code and minimizes the user interaction
needed to adhere to the I
2
C protocol. The smart mode accomplishes this by automatically issuing an ACK
or NACK (based on the content of CTRLB.ACKACT) as soon as DATA.DATA is read.
28.6.3.3 4-Wire Mode
Writing a '1' to the Pin Usage bit in the Control A register (CTRLA.PINOUT) will enable 4-wire mode
operation. In this mode, the internal I
2
C tri-state drivers are bypassed, and an external I
2
C compliant tri-
state driver is needed when connecting to an I
2
C bus.
SAM D21 Family
SERCOM I2C – Inter-Integrated Circuit
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 565